1. Field of the Invention
The present invention pertains to data transfers in a computer system. More particularly, this invention relates to transferring data between two buses in a computer system using a bus bridge.
2. Background
As technology has progressed, the number, types, and functional power of computer system components has steadily increased. Given the large number and different operating speeds of different components, modern computer systems typically include two, three, or more buses for coupling together the different components.
One device commonly used to couple together two different buses is referred to as a bus bridge. Typically, requests transferred between buses via a bus bridge can be either posted or non-posted. A posted request refers to a request from a source agent on a source bus which has been accepted by the bridge, and the source agent knows that the request will be provided to the target agent on the target bus, regardless of whether the request has been actually delivered to the target agent yet or whether it is pending in a buffer in the bridge. A non-posted request refers to a request which is being transferred through the bus bridge and the source agent does not know whether the request can be delivered to the target agent until it is actually received by the target agent.
One important goal in designing a bus bridge is to provide an efficient communication path between the two buses. However, one problem that can arise when using a bus bridge is referred to as "thrashing". Thrashing refers to a situation where both of the buses are fully utilized, but very few, if any, data transfers between the two buses can progress. This situation can arise, for example, in a system involving a bus bridge coupling together a system bus and a Peripheral Component Interconnect (PCI) bus, such as a bus in accordance with the PCI Local Bus Specification, Version 2.1, published Jun. 1, 1995. If an agent on the PCI bus is writing to main memory on the system bus and posting in the bus bridge is disabled, then if a processor on the system bus is repetitively issuing requests targeting the PCI bus, the requests by the agent and the processor can prevent the requests of the other from progressing. When thrashing occurs, data transfers between the two buses cannot be made. The thrashing situation may eventually work itself out by chance, but it can also persist indefinitely. Furthermore, the requests which are causing the thrashing to occur may also lock up the two buses such that no other requests can be issued by other agents on those buses. Thus, it would be beneficial to provide a system which reduces thrashing in a computer system.
One solution to this thrashing problem is to disable the posting buffers as soon as the thrashing situation is detected. However, this can result in keeping a postable write transaction from an I/O bus from being able to be completed by posting data. This forces the I/O bus to slow to the speed necessary to synchronize it to the system bus, via the bus bridge, in order to perform a nonpostable transaction, thereby reducing the speed at which the transaction is completed. Thus, it would be beneficial to provide a system which reduces the period of time during which the posting of data from the I/O bus to the system bus is disabled.
As will be described in more detail below, the present invention provides a method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge that achieves these and other desired results which will be apparent to those skilled in the art from the description to follow.